We have intercepted a coded Imperial message from the Klockars system!
 JK> I recently jumped into the thread on the internet and tried to clear
 JK> up what the bet was about. Perhaps I should say something here as
 JK> well.
 JK> What started the whole thing was that someone (not KA I think) said
 JK> that a 32 MHz '040 executed more instructions per second than a
 JK> 486Dx/66. The argument was that the '040 was clock doubled as well and
 JK> thus could execute something like 64/1.3 MIPS against the 486's
 JK> 66/1.8. Hendrik jumped in saying that that was not true, which not
 JK> everyone agreed with as we have all heard.  ;-)

 JK> It _is_ not true.

The MC68040 is capable of sustaining 1.25 cycles per instruction against the 
i486DX's slower 1.75 cycles. This places the 68040's MIPS rating a significant 
amount above it's counterpart. With the DX2 operating at 66Mhz, the MIPS rating 
of the 486 is doubled, with the number of cycles per instruction is exactly the 
same. (You are not improving the chip, after all).

When dealing with VAX MIPS, which is a DREADFULLY false way to make comparisons 
between non-RISC processors, the DX266 is capable of 50% more instruction 
throughput than the 68040.

About this you are undoubtedly correct.

This does not however escape the fact that the 68040 operates via both 32Mhz 
and 64Mhz cycles which allows the pipeline to deal with these extremely heavy 
instructions at nearly twice the rate possible at only 32Mhz. The instruction 
units might not operate at 64Mhz, but the pipeline is allowed to graduate them 
at just 1 cycle for almost all instructions, placing it's MIPS/CLOCK ratio WAY 
above the 486 in any of it's disguises.

This is a very advanced form of double-clocking and does very much count as 
such. Motorola will explain in great detail to those who hold doubt.

 JK> Did I really see someone here a couple of messages ago claiming the
 JK> '040 was faster than the Pentium? That's of course ridiculous.

However, my own brief messages comparing the power of the various Intel / 
Motorola technologies were not nearly as rediculous as you seem to infer.

*-------------------------------------------------------------------------*

Here is a list of instruction throughputs.

68040       1.25        cycles/ins
486         1.75        cycles/ins
Pentium     1.10        cycles/ins

*-------------------------------------------------------------------------*

When calculated in MIPS at the various clockrates, this gives the following.

68040       @ 32Mhz     25 MIPS
486DX       @ 33Mhz     18 MIPS
486DX2      @ 66Mhz     37 MIPS
Pentium-60  @ 60Mhz     54 MIPS
Pentium-90  @ 90Mhz     80 MIPS

THOSE are the figures people are swearing by. Pity they do not represent the 
power and speed of the Processors themselves. To calculate this information, we 
must proceed a further 2 stages...

*-------------------------------------------------------------------------*

When calculated in MIPS at the SAME clockrates, this gives the following.

68040       @ 33Mhz     26 MIPS
486DX       @ 33Mhz     18 MIPS
Pentium     @ 33Mhz     30 MIPS

These are the ACTUAL capabilities of the various technologies described. The 
68040 when compared on even ground is WAY ahead of the 486 and just behind the 
Pentium in plain MIPS.

*-------------------------------------------------------------------------*

Now for the really important bit...

*-------------------------------------------------------------------------*

It is well known that the 80x86 family suffers SEVERELY from it's weak 
instruction set, lack of registers, memory segmentation and lack of true 32-bit 
capability. Anything used to get round these problems has been an indirect 
enhancement which has failed to achieve the results expected of a true 32-bit 
chip.

Examples of this are:-

a) 486 'protected mode' nearly emulates 68000's memory space (slows down the 
execution unit as well).

c) Heavy reliance on cache/bus interface due to importance of ax/bx registers 
and being constantly trashed as a result.

b) Slow floating-point causes integer bottlenecks.


The result is that the MOPS rating (Millions of Operations Per Second) for the 
486/Pentium is only 2-4 times that of it's MIPS value. For a CISC chip, this is 
not good.

Also, due to the direct Pentium/486 compatibility and lack of effective Pentium 
enhanced instructions, the MIPS:MOPS values are directly
proportional on both chips, so this is correct to within about 10% error.

*-------------------------------------------------------------------------*

The 68040's architecture and instruction set is in a different league from the 
that of the Intel 80x86 family. That INCLUDES the Pentium.

With 15 free-access 32-bit registers, linear address space and addressing modes 
to die for (at or around 1 cycle each!) the MOPS value (Millions of Operations 
Per Second) assigned to the chip is immense, effectively equivalent to between 
4 and 8 times it's assigned RISC MIPS value. If you don't believe me, check it 
out. THAT is where all the work went on the 68040 and THAT is what is so good 
about it. Forget VAX (RISC) MIPS - use CISC MOPS instead - that's what they are 
there for. Anybody who dares to claim that this approach, when estimating the 
true power of a processor, is irrelevant, obviously does not understand silicon 
and the gross injustice done by applying weak VAX MIPS to a chip with such a 
non-RISC instruction set.

*-------------------------------------------------------------------------*

All of my notes and figures are based on the same clockrate and the resulting 
MOPS value at this rate. I don't care if somebody dips the chip in liquid 
nitrogen and makes the PCB with superconducting material with a 200Mhz clock as 
this can be done with any design - the architecture defines the true speed of 
the chip and always will.

This is why the 32MHz DSP56000 is only 16Mips and can murder a 486DX2 66Mhz at 
everything from 3D geometry to image processing - it's operating at an average 
of 96 MOPS, with up to 7 RISC operations per instruction! THIS is where the 
power lies.

 JK> Now the '040 is probably a much more complicated chip than the 486,
 JK> which might explain why Motorola have not tried any Dx2:ing.

You could say the same applies to the Pentium.

More importantly, the 68060 being true superscalar, outperforms both by a very 
good margin - even in RISC MIPS. Who needs DX2 when you can just build a good 
chip instead?

That's why the 486 was double clocked - they couldn't improve the crap 
architecture without making it incompatible.

:)


Cheers,

    Doug.

