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# -------------------------------------------------------------------
# TOM                                   (c) Copyright 1996 Nat! & KKP
# -------------------------------------------------------------------
# These are some of the results/guesses that Klaus and Nat! found
# out about the Jaguar with a few helpful hints by other people, 
# who'd prefer to remain anonymous. 
#
# Since we are not under NDA or anything from Atari we feel free to 
# give this to you for educational purposes only.
#
# Please note, that this is not official documentation from Atari
# or derived work thereof (both of us have never seen the Atari docs)
# and Atari isn't connected with this in any way.
#
# Please use this informationphile as a starting point for your own
# exploration and not as a reference. If you find anything inaccurate,
# missing, needing more explanation etc. by all means please write
# to us:
#    nat@zumdick.rhein-main.de
# or
#    kkp@gamma.dou.dk
#
# If you could do us a small favor, don't use this information for
# those lame flamewars on r.g.v.a or the mailing list.
#
# HTML soon ?
# -------------------------------------------------------------------
# $Id: tom.txt,v 1.8 1996/02/11 23:00:44 nat Exp $
# -------------------------------------------------------------------
Here are the leftovers of TOM that aren't described in the OP, Blitter
or RISC dox.


MEMORY CONFIGURATION:
====================

RW: MEMCON1 ($F00000)
~~~~~~~~~~~~~~~~~~~~~
  16        12         8         4         0
   +---------^---------+--+----+-^--+------+
   |      unknown      |f | ram| rom|  unk | 
   +-------------------+--+----+----+------+
      15...........8    7  6..5 4..3  2...0

   unknown (unk) :

   rom:
      Romspeed are set to zero on reset.
      0: 10 clock cycles  
      1:  8  "      "     
      2:  6  "      "     
      3:  5  "      "

   ram:
      0:  slowest
      1:  ...
      2:  ...
      3:  zero wait state
      
      sets RAM access speeds, probably you can set the number of 
      wait states. 

   fastrom (f):
      FASTROM (2 cycles for ROM access)  
      For testing...

      Default value: $1861


RW: MEMCON2 ($F00002)
~~~~~~~~~~~~~~~~~~~~~
  16        12         8         4         0
   +---------^---------+---------^---------+
   |                 unknown               | 
   +-------------------+-------------------+
      15.................................0

   Seems to configure the endianness of the system and
   other stuff. Probably the number of MBs available and so forth.
   Usual value apparently: $35CC, ($35DD for Intel chips (?))

   

INTERRUPT CONTROL:
=================

This controls, I believe, the interrupts that TOM generates to external
destinations (f.e. the 68K).


W: INT1 ($F000E0):
~~~~~~~~~~~~~~~~~~
  16        12         8         4         0
   +---------^---------+---------^---------+
   |       latches     |       enable      | 
   +-------------------+-------------------+
           15...8              7...0

   enable:
      bit 0:   LEVEL 0 IRQ enable  (VBLANK)
      bit 1:   LEVEL 1 IRQ enable      
      bit 2:   LEVEL 2 IRQ enable  (HBLANK - OP-Flag)
      bit 3:   LEVEL 3 IRQ enable  (TIMER)    
      bit 4:   LEVEL 4 IRQ enable      
      bit 5:   unused      
      bit 6:   unused

   Enable by setting the appropriate bits

   latches:
      bit 8:   LEVEL 0 IRQ         (VBLANK)
      bit 9:   LEVEL 1 IRQ       
      bit10:   LEVEL 2 IRQ         (HBLANK OP-Flag)
      bit11:   LEVEL 3 IRQ         (TIMER)
      bit12:   LEVEL 4 IRQ       
      bit13:   unused      
      bit14:   unused

   Clear the latch by setting the appropriate bit.

   (List of other possible IRQ sources (just guessing)
      Blitter idle,
      OP GPU Object
      Host IRQ (from 68K)     
   )


R: INT1 ($F000E0):
~~~~~~~~~~~~~~~~~~
  16        12         8         4         0
   +---------^---------+---------^---------+
   |       unused      |       active      | 
   +-------------------+-------------------+
           15...8              7...0

   active:
      bit 0:   LEVEL 0 IRQ enable  (VBLANK)
      bit 1:   LEVEL 1 IRQ enable      
      bit 2:   LEVEL 2 IRQ enable  (HBLANK OP-Flag)
      bit 3:   LEVEL 3 IRQ enable  (TIMER)    
      bit 4:   LEVEL 4 IRQ enable      
      bit 5:   unused      
      bit 6:   unused

   Poll this register to check, which interrupts generated the IRQ.
   I think there's a possibility that more than one bit is set.


W:  INT2 ($F000E2):
~~~~~~~~~~~~~~~~~~
  16        12         8         4         0
   +---------^---------+---------^---------+
   |               restart                 | 
   +---------------------------------------+

restart:   
   Restart a suspended GPU. The GPU is suspended during 68K interrupt
   processing. There is a feature (bug) when the IRQ is processed by 
   the 68K instead of the GPU. As soon as the interrupt "goes up" the 
   GPU (but not the DSP) is halted and then, if the interrupt is not 
   enabled the GPU remains halted! It will restart after a write to 
   INT2, but ONLY if the interrupt's latch bit (INT1 upper byte) has 
   been cleared.


PROGRAMMABLE TIMER:
===================

RW: PIT ($F00050)
~~~~~~~~~~~~~~~~~
 32       28        24        20       16       12        8        4        0
  +--------^---------^---------^--------^--------^--------^--------^--------+
  |                                   value                                 |
  +-------------------------------------------------------------------------+

value:

   You load up the counter and it starts as soon as you write the low 
   word. It will generate a LEVEL3 IRQ when it reaches zero, and then 
   will restart with the value written to it. It will, when it reaches 
   zero, again field an IRQ.
   The frequency with which this timer counts down is the CPU frequency.
   A value of $195E200 is therefore approximately one second.
</PRE>
<HR>
<address><a href="mailto:nat@zumdick.rhein-main.de">Nat! (nat@zumdick.rhein-main.de)</a></address>
<address><a href="mailto:kkp@gamma.dou.dk">Klaus (kkp@gamma.dou.dk)</a></address>
<P>
$Id: tom.txt,v 1.8 1996/02/11 23:00:44 nat Exp $
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